(a) Field of the Invention
The present invention relates to an image optimized rolling cache system.
(b) Description of the Related Art
A filed-programmable gate array (FPGA) serves as an optimized hardware accelerator for real time image processing and a vision application. However, if image resolution is increased, there is a need to use an external SDR/DDR memory. A predetermined pixel access pattern used in most algorithms reduces a bandwidth thereof resulting from an access delay increase.
An efficient cache design is very important for a real time intensive application. An effect resulting from the cache design is changed according to a spatial area and a time area of data access. The spatial area in image processing represents horizontally and vertically two-dimensional neighbor pixels. However, in general, since a vertical area cannot be defined in an existing cache used for a processor, an efficient cache design is difficult.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.